verilog - 4 bit register with enable and asynchronous reset

Question

I am modelling a 4 bit register with enable and asynchronous reset . The register has three one bit input namely clk, reset and enable, one four bit input, D and one four bit output Q using verilog. Here is my design and testbench. Design

    module fourbitreg(D,clk,reset,enable, Q);
    input[3:0] D; // Data input
    input clk,reset,enable;
    output[3:0] Q; // output Q
    reg[3:0] Q;
    always @(posedge clk or posedge reset)
    begin
            if(reset)
                    Q <= 4’b0;
            else if (enable)
                    Q <= D;
    end
    endmodule

Testbench

    module four_bitreg_tb;
      reg [3:0] D;
    reg clk,reset,enable;
    wire[3:0]Q;
    always #5 clk = ~clk;
      fourbitreg uut(.D(D),.clk(clk),.reset(reset),.enable(enable),.Q(Q));
    initial begin
        $monitor("time=",$time,"D=%b  reset =%d  enable =%d  Q=%b",D,reset,enable,Q);
        $dumpfile("dump.vcd");
        $dumpvars;
        reset <= 0;
        enable <= 0;
        D <=  4'b0000; 
        #5 
        D <= 4'b0001; 
        reset <= 0;
        enable <= 1;
        #5
        D <= 4'b0010; 
        reset <= 1;
        enable <= 0;
        #5
        D <= 4'b0011; 
        reset <= 1;
        enable <=1;
        #5
        D <= 4'b0100; 
        reset <= 0;
            enable <= 0;
        #5
        D <= 4'b0101; 
        reset <= 0;
            enable <= 1;
        #5
        D <= 4'b0110; 
        reset <= 1;
            enable <= 0;
        #5
        D <= 4'b0111; 
        reset <= 1;
            enable <= 1;
        #5
        D <= 4'b1000; 
        reset <= 0;
            enable <= 0;
        #5
        D <= 4'b1001; 
        reset <= 0;
            enable <= 1;
        #5
        D <= 4'b1010; 
        reset <= 1;
            enable <= 0;
        #5
        D <= 4'b1011; 
        reset <= 1;
            enable <= 1;
        #5
        D <= 4'b1100; 
        reset <= 0;
            enable <= 0;
        #5
        D <= 4'b1101; 
        reset <= 0;
            enable <= 1;
        #5
        D <= 4'b1110; 
        reset <= 1;
            enable <= 0;
        #5
        D <= 4'b1111;
        reset <= 1;
            enable <= 1;
        #20 $finish;
    end
    endmodule

I am getting the following errors while compiling the code.

    4bitreg.v:9: syntax error
    I give up.

I didn't find any issue with the code.

question from:https://stackoverflow.com/questions/65713489/4-bit-register-with-enable-and-asynchronous-reset

Answer 1

Q <= 4’b0; at line 9 should be changed as Q <= 4'b0;.